US 2026/0173368 A1Published application

Manufacturing method for memory device, memory device, and memory cell

AssigneeWuhan Xinxin Semiconductor Manufacturing Co., Ltd.

InventorsFengcong GONG, Kaiwei CAO

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Abstract

A manufacturing method for a memory device, a memory device, and a memory cell. The manufacturing method includes: providing a semiconductor substrate, which includes a substrate and a hard mask layer; defining first trenches in the substrate, some of which are located in a memory region and others are located in a lead-out region; forming a gate insulating layer and a semi-floating gate on a bottom of each base trench, where a portion of the semi-floating gate contacts the substrate, and another portion is isolated from the substrate; and forming an inter-gate dielectric layer and a first gate layer in each first trench, removing a portion of the first gate layer in each first trench in the memory region to form a control gate, and retaining the first gate layer in each first trenches in the lead-out region as a lead-out line.

Claims25

Dependent claims

A manufacturing method for a memory device, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a hard mask layer on the substrate;
defining a plurality of first trenches in active areas of the substrate from the hard mask layer;
wherein some of the plurality of first trenches are located in a memory region, and others of the plurality of first trenches are located in a lead-out region;
a portion of each first trench in the substrate is defined as a base trench;
forming a gate insulating layer and a semi-floating gate on a bottom of each base trench;
wherein a portion of the semi-floating gate is in contact with the substrate, and another portion of the semi-floating gate is isolated from the substrate by the gate insulating layer;
and
forming an inter-gate dielectric layer and a first gate layer in each first trench, removing a portion of the first gate layer in each first trench in the memory region to form a control gate of a corresponding memory cell, and retaining the first gate layer in each first trenches in the lead-out region as a lead-out line of a corresponding memory cell;
wherein the lead-out line is connected to the control gates of memory cells in a same row as the lead-out line.

6 more elements

A memory device, comprising:

a substrate;
a plurality of base trenches;
wherein each base trench extends from a surface of the substrate toward the substrate;
some of the plurality of base trenches are located in a memory region, and others of the plurality of base trenches are located in a lead-out region;
an inner wall on a bottom of each base trench is arranged with a gate insulating layer;
a semi-floating gate;
wherein the semi-floating gate is located on the bottom of the base trench;
a portion of the semi-floating gate is isolated from the substrate by the gate insulating layer, and another portion of the semi-floating gate is in contact with the substrate;
an inter-gate dielectric layer, covering the semi-floating gate;
and
a first gate layer, formed on the inter-gate dielectric layer;
wherein the first gate layer in the memory region constitutes a control gate of a corresponding memory cell in the memory device, and the first gate layer in the lead-out region serves as a lead-out line, which connects the control gates of memory cells in a same row.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/536,254Filed 11 Feb 2026
Priority: CN 202311044576.316 Aug 2023
Published: 18 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor
H10B 12/053
Making the transistor: the transistor being at least partially in a trench in the substrate