Lane alignment for symbol multiplexed wired communication systems
AssigneeXilinx, Inc.
InventorMartin RIIS
Life of this patent
Estimating the term…
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AssigneeXilinx, Inc.
InventorMartin RIIS
Estimating the term…
Alignment detection circuitry is disclosed that include a buffer configured to output a data stream of multiplexed groups of symbols from multiple data lanes and a set of correlators configured to determine physical link skew from one data lane of the multiple data lanes, wherein the physical link skew from the one data lane is known to equal the physical link skew on each data lane, assuming each data lane is transmitted over the same physical link. The alignment detection circuitry may also include anti-aliasing circuitry configured to extract a unique marker of the alignment marker to detect common marker aliasing by comparing the extracted unique marker to a known unique marker. Anti-aliasing circuitry may also be configured to use common marker detection status of adjacent data lanes of the multiple data lanes to detect common marker aliasing determined by a detection delay between the adjacent data lanes.
Alignment detection circuitry comprising:
Alignment detection circuitry comprising:
Alignment detection circuitry comprising:
Dependencies are inferred from the claim text.