Memory system and nonvolatile memory device capable of compressing data from a memory plane and outputting data in parallel

A method of operating a nonvolatile memory device, wherein the nonvolatile memory device comprises a memory cell array including a first memory plane and a second memory plane, a first page buffer circuit and a second page buffer circuit connected with the first memory plane and the second memory plane, respectively, through respective of bit-lines, a first compression engine and a second compression engine connected with the first page buffer circuit and the second page buffer circuit through respective local data lines, and a data input/output (I/O) circuit connected with the first page buffer circuit and the second page buffer circuit through global data lines separated from the local data lines, the method comprising:

• receiving, by the first compression engine and the second compression engine, soft decision data from the first page buffer circuit and the second page buffer circuit;
• compressing, by the first compression engine and the second compression engine, the received soft decision data;
• and
• outputting, by the first page buffer circuit and the second page buffer circuit, the compressed soft decision data through the data I/O circuit,
• wherein compressing the received soft decision data is performed in parallel with outputting the compressed soft decision data through the data I/O circuit.

A nonvolatile memory device comprising:

• a memory cell array including a plurality of memory planes;
• a plurality of page buffer circuits, each page buffer circuit of the plurality of page buffer circuits connected with a respective memory plane of the plurality of memory planes through a respective plurality of bit-lines;
• a plurality of compression engines, each compression engine of the plurality of compression engines connected with a respective page buffer circuit of the plurality of page buffer circuits through a respective plurality of local data lines;
• a data input/output (I/O) circuit connected with the plurality of page buffer circuits through a plurality of global data lines separated from the plurality of local data lines;
• and
• a control circuit configured to:
• control each compression engine of one or more compression engines among the plurality of compression engines to perform an encoding operation by receiving soft decision data from a plurality of target cache latches of the plurality of cache latches and by compressing the received soft decision data;
• and
• control one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I/O circuit, the output operation being performed in parallel with the encoding operation, the one or more page buffer circuits corresponding to the one or more compression engines.