Low power filtering of pulse density modulated data using a digital filter with gray encoding/decoding
AssigneeSTMicroelectronics International N.V.
InventorsAnkur BAL, Sharad GUPTA
Life of this patent
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Abstract
A sigma-delta (ΣΔ) analog to digital converter (ADC) circuit receives an analog signal and outputs a pulse density modulated digital signal. A digital filter filters a sequence of data values for the pulse density modulated digital signal. The digital filter includes a multi-stage delay line, an encoder circuit configured to encode data values of the sequence of data values for input to the multi-stage delay line, and decoder circuits configured to decode data values output from corresponding taps of the multi-stage delay line. The encoder may be a Binary to Gray code encoder and the decoder may be a Gray to Binary code decoder.
Claims21
A circuit, comprising:
- a sigma-delta (ΣΔ) analog to digital converter (ADC) circuit having an input configured to receive an analog signal and an output configured to generate a pulse density modulated digital signal including a sequence of data values;
- and
- a digital filter configured to receive the sequence of data values for the pulse density modulated digital signal, wherein the digital filter includes a multi-stage delay line, an encoder circuit configured to encode data values of the sequence of data values for input to the multi-stage delay line, and a plurality of decoder circuits configured to decode data values output from corresponding taps of the multi-stage delay line.
A digital filter circuit, comprising:
- an input configured to receive a filter input signal comprising a sequence of data values;
- an encoder circuit configured to encode data values of the sequence of data values;
- a multi-stage delay line having an input configured to receive encoded data values output from the encoder circuit;
- a plurality of decoder circuits configured to decode data values output from corresponding taps of the multi-stage delay line;
- and
- a summation circuit configured to add decoded data values output from the plurality of decoder circuits to generate a filter output signal.
A digital filter circuit, comprising:
- an input configured to receive a filter input signal comprising a sequence of input data values;
- an output configured to generate a filter output signal comprising a sequence of output data values;
- an encoder circuit configured to encode data values of the sequence of output data values;
- a multi-stage delay line having an input configured to receive encoded data values output from the encoder circuit;
- a plurality of decoder circuits configured to decode data values output from corresponding taps of the multi-stage delay line;
- and
- a summation circuit configured to subtract from the filter input signal the decoded data values output from the plurality of decoder circuits to generate the filter output signal.
Dependencies are inferred from the claim text.