Analog-to-digital converter (adc) architectures for high resolution and energy efficiency
AssigneeArizona Board of Regents on behalf of Arizona State University
InventorArindam SANYAL
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Abstract
A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.
Claims20
A method of converting an analog signal to a digital signal using a low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface, the method comprising:
- obtaining, by a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC, an input analog signal to produce a first output;
- obtaining, by a voltage-controlled oscillator (VCO)-ADC, the first output from the first stage to produce a second output;
- and
- obtaining, by a calibration stage, the second output to estimate and track interstage gain across a process-voltage-temperature (PVT),
- wherein the calibration stage comprises a foreground calibration stage that operates only at device start up to receive the first output and the second output to extract an initial interstage gain error and corrects the initial interstage gain error and a background calibration stage that corrects continued instances of the interstage gain error that varies with time, voltage, and temperature of the device.
A method of converting an analog signal to a digital using a low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) system, the method comprising:
- obtaining, by a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC, an input analog signal to produce a first output;
- obtaining, by an artificial intelligence or a machine learning engine-assisted voltage-controlled oscillator (VCO)-ADC, the first output to produce a second output;
- and
- obtaining, by a calibration stage, the second output to estimate and track interstage gain across a process-voltage-temperature (PVT),
- wherein the calibration stage comprises a foreground calibration stage that operates only at device start up to receive the first output and the second output to extract an initial interstage gain error and corrects the initial interstage gain error and a background calibration stage that corrects continued instances of the interstage gain error that varies with time, voltage, and temperature of the device.
A method of operating a radio comprising:
- obtaining, by an antenna of the radio, a radio signal;
- obtaining, by a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC, the radio signal to produce a first output;
- obtaining, by a voltage-controlled oscillator (VCO)-ADC, the first output from the first stage to produce a second output;
- and
- obtaining, by a calibration stage, the second output to estimate and track interstage gain across a process-voltage-temperature (PVT),
- wherein the calibration stage comprises a foreground calibration stage that operates only at device start up to receive the first output and the second output to extract an initial interstage gain error and corrects the initial interstage gain error and a background calibration stage that corrects continued instances of the interstage gain error that varies with time, voltage, and temperature of the device.
Dependencies are inferred from the claim text.