Top-Plate Sampling Circuitry

A top-plate sampling circuitry for sampling a voltage input signal, the circuitry comprising:

• a sampling transistor and a sampling capacitor, wherein the sampling transistor connects the voltage input signal to a top plate of the sampling capacitor;
• wherein the sampling transistor is operable as a switch by a gate node according to a tracking phase and a holding phase;
• wherein, during the tracking phase, the sampling transistor is closed and conducts the voltage input signal onto the top plate;
• and wherein, upon switching from the tracking phase to the holding phase, the sampling transistor is opened such that the voltage input signal is sampled on the top plate as a voltage output signal, and maintained during the holding phase;
• a bootstrapper sub-circuitry configured to bootstrap the voltage input signal with a fixed surplus voltage to a bootstrapped voltage, and to, during the tracking phase, provide the bootstrapped voltage to the gate node, thereby keeping the sampling transistor closed by the fixed surplus voltage;
• and
• a gate switch between the gate node and a fixed reference voltage, wherein the gate switch is configured to transition from open to closed during the switching, thereby opening the sampling transistor at a sampling time;
• wherein the circuitry is further configured to, during the switching from the tracking phase to the holding phase, provide a resistive coupling between the bootstrapped voltage and the gate node, thereby allowing a difference between a gate voltage at the gate node and a source voltage at a source node to drop below a threshold voltage of the sampling transistor so as to open the sampling transistor.