Fractional divider calibration with dual digital control delay circuits

A system comprising:

• a divider configured to divide an input clock signal to generate an integer output divider (IOD) signal;
• a circuit comprising:
• a first digital control delay (DCD) circuit configured to delay the IOD signal to generate a first delayed IOD signal;
• a second DCD circuit configured to delay the first delayed IOD signal to generate a second delayed IOD signal;
• an edge sampler configured to compare an edge of the second delayed IOD signal with an edge of the input clock signal;
• and
• a controller configured to calibrate the first DCD circuit based on a result of the comparison between the edge of the second delayed IOD signal with the edge of the input clock signal.

A method comprising:

• dividing an input clock signal to generate an integer output divider (IOD) signal;
• delaying the IOD signal to generate a first delayed IOD signal;
• delaying the first delayed IOD signal to generate a second delayed IOD signal;
• comparing an edge of the second delayed IOD signal with an edge of the input clock signal;
• and
• calibrating a digital control delay (DCD) circuit that generated the first delayed IOD signal, wherein the calibration is based on a result of the comparison between the edge of the second delayed IOD signal with the edge of the input clock signal.