Inverter in gallium-nitride technology
OwnerKatia Samperi, Urmimala Chatterjee +1inventors
InventorsKatia Samperi, Urmimala Chatterjee, Salvatore Pennisi
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Abstract
A Gallium-Nitride inverter is provided using only n-type enhancement mode transistors to facilitate achieving Direct-Coupled-FET (DCFL) logic. The Gallium-Nitride inverter includes a first e-mode n-type GaN input transistor, which may be connected to a pull-up network. The pull-up network includes at least three e-mode n-type GaN transistors, such as a first e-mode n-type GaN transistor, a second e-mode n-type GaN transistor including a source and a drain, and a third e-mode n-type GaN transistor. The third e-mode n-type GaN transistor may be connected to the first drain of the e-mode n-type GaN input transistor.
Claims20
A Gallium-Nitride inverter comprising:
- a first e-mode n-type GaN input transistor, wherein the first e-mode n-type GaN input transistor includes:
- a first gate, wherein the first gate is an input of the inverter;
- and
- a first drain, wherein the first drain is connected to an output of the inverter and connected to a pull-up network, wherein the pull-up network includes at least three e-mode n-type GaN transistors, the at least three e-mode n-type GaN transistors of the pull-up network include:
- a first e-mode n-type GaN transistor including a gate and a drain, wherein the first e-mode n-type GaN transistor is configured as a diode by connecting the first e-mode n-type GaN transistor gate to the first e-mode n-type GaN transistor drain,
- a second e-mode n-type GaN transistor including a source and a drain, wherein the second e-mode n-type GaN transistor is configured as a capacitor by connecting the second e-mode n-type GaN transistor source to the second e-mode n-type GaN transistor drain, and
- a third e-mode n-type GaN transistor including a gate, a source, and a drain, wherein
- the third e-mode n-type GaN transistor gate is connected to a source of the first e-mode n-type GaN transistor and to a gate of the second e-mode n-type GaN transistor, the third e-mode n-type GaN transistor drain is connected to the first e-mode n-type GaN transistor gate, and the third e-mode n-type GaN transistor source is connected to the second e-mode n-type GaN transistor source and the second e-mode n-type GaN transistor drain, and to the first drain of the first e-mode n-type GaN input transistor.
A logic gate comprising an inverter, the inverter is a Gallium-Nitride inverter, wherein the inverter comprises:
- a first e-mode n-type GaN input transistor, wherein the first e-mode n-type GaN input transistor includes:
- a first gate, wherein the first gate is an input of the inverter;
- and
- a first drain, wherein the first drain is connected to an output of the inverter and connected to a pull-up network, wherein the pull-up network includes at least three e-mode n-type GaN transistors, the at least three e-mode n-type GaN transistors of the pull-up network include:
- a first e-mode n-type GaN transistor including a gate and a drain, wherein the first e-mode n-type GaN transistor is configured as a diode by connecting the first e-mode n-type GaN transistor gate to the first e-mode n-type GaN transistor drain,
- a second e-mode n-type GaN transistor including a source and a drain, wherein the second e-mode n-type GaN transistor is configured as a capacitor by connecting the second e-mode n-type GaN transistor source to the second e-mode n-type GaN transistor drain, and
- a third e-mode n-type GaN transistor including a gate, a source, and a drain, wherein the third e-mode n-type GaN transistor gate is connected to a source of the first e-mode n-type GaN transistor and to a gate of the second e-mode n-type GaN transistor,
- the third e-mode n-type GaN transistor drain is connected to the first e-mode n-type GaN transistor gate, and the third e-mode n-type GaN transistor source is connected to the second e-mode n-type GaN transistor source and the second e-mode n-type GaN transistor drain, and to the first drain of the first e-mode n-type GaN input transistor.
Dependencies are inferred from the claim text.