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AssigneeNexperia B.V.
InventorsRahul Shaw, Gaurav Bahirvani
Estimating the term…
A continuous time comparator including a first Field Effect Transistor, (FET) for receiving a first input signal, and a second FET for receiving a second signal, a first branch includes a first transistor and a second branch includes a second transistor, the first branch is connected to the first FET and the second branch is connected to the second FET, a first dynamic clamp circuitry connected in parallel over the first branch, the first dynamic clamp circuitry, dynamically clamps a voltage at a gate of a first output transistor, and a second dynamic clamp circuitry connected in parallel over the second branch, the second dynamic clamp circuitry, dynamically clamps a voltage at a gate of a second output transistor, the first and second output transistors provide an output of the comparator and for an inverting output of the comparator.
The continuous time comparator in accordance with claim 1, further comprising a cross-coupled first and second bias transistors connected in series with the first and second output transistors.
The continuous time comparator in accordance with claim 1, wherein the first transistor of the first branch and the second transistor of the second branch are cross-coupled.
The continuous time comparator in accordance with claim 1, wherein each of the first dynamic clamp circuitry and the second dynamic clamp circuitry comprises a clamping transistor connected in series with a clamp control transistor.
The continuous time comparator in accordance with claim 1, wherein the comparator is implemented on a semiconductor die.
An integrated circuit (IC) comprising a continuous time comparator in accordance with claim 1.
A method of operating a continuous time comparator in accordance with claim 1, wherein the method comprises the steps of:
Dependencies are inferred from the claim text.