US 2026/0171987 A1Published application

Voltage comparison circuit, related integrated circuit and method

AssigneeSTMicroelectronics International N.V.

InventorsMahmoud Savadkouhi, Fulvio Schiappelli

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Abstract

According to an embodiment, a voltage comparison circuit comprises terminals for receiving an input voltage and a supply voltage. A measurement circuit generates a measurement signal and comprises first and second resistances coupled in series. An n-channel Field-Effect Transistor is coupled in series with the first resistance, with a gate terminal coupled to a bias voltage source. Collectors of first and second NPN bipolar transistors are coupled to the supply voltage terminal, and bases are coupled to a node between the resistances. A third resistance is coupled between an emitter of the first NPN bipolar transistor and ground, and a fourth resistance is coupled between emitters of the transistors. A comparison circuit determines whether a first current through the first NPN bipolar transistor exceeds a second current through the second NPN bipolar transistor and asserts a comparison signal accordingly. The n-channel Field-Effect Transistor limits the measurement signal.

Claims20

Dependent claims

A voltage comparison circuit configured to assert a comparison signal in response to determining that an input voltage exceeds a given threshold voltage, the voltage comparison circuit comprising:

a first terminal and a second terminal configured to receive the input voltage;
a third terminal configured to receive a supply voltage;
a measurement circuit configured to generate a measurement signal indicative of the input voltage, wherein the measurement circuit comprises a first resistance coupled between the first terminal and a first node, and a second resistance coupled between the first node and the second terminal, wherein the measurement signal corresponds to a voltage at the second resistance;
a first NPN bipolar transistor and a second NPN bipolar transistor, each having a collector terminal, an emitter terminal, and a base terminal, wherein the collector terminals of the first NPN bipolar transistor and the second NPN bipolar transistor are coupled to the third terminal, and the base terminals of the first NPN bipolar transistor and the second NPN bipolar transistor are coupled to the first node, wherein an emitter area of the second NPN bipolar transistor is greater than an emitter area of the first NPN bipolar transistor;
a third resistance coupled between the emitter terminal of the first NPN bipolar transistor and the second terminal, and a fourth resistance coupled between the emitter terminal of the second NPN bipolar transistor and the emitter terminal of the first NPN bipolar transistor;
and
a comparison circuit configured to:
determine whether a first current flowing through the collector terminal of the first NPN bipolar transistor is greater than a second current flowing through the collector terminal of the second NPN bipolar transistor,
assert the comparison signal in response to determining that the first current is greater than the second current, and
de-assert the comparison signal in response to determining that the first current is smaller than the second current,
wherein the measurement circuit comprises an n-channel Field-Effect Transistor (FET), wherein the n-channel FET and the first resistance are coupled in series between the first terminal and the first node, wherein a gate terminal of the n-channel FET is coupled to a bias voltage source.

8 more elements

An integrated circuit comprising a voltage comparison circuit configured to assert a comparison signal in response to determining that an input voltage exceeds a given threshold voltage, the voltage comparison circuit comprising:

a first terminal and a second terminal configured to receive the input voltage;
a third terminal configured to receive a supply voltage;
a measurement circuit configured to generate a measurement signal indicative of the input voltage, wherein the measurement circuit comprises a first resistance coupled between the first terminal and a first node, a second resistance coupled between the first node and the second terminal, and an n-channel Field-Effect Transistor (FET) coupled in series with the first resistance between the first terminal and the first node, wherein a gate terminal of the n-channel FET is coupled to a bias voltage source, wherein the measurement signal corresponds to a voltage at the second resistance;
a first NPN bipolar transistor and a second NPN bipolar transistor, each having a collector terminal, an emitter terminal, and a base terminal, wherein the collector terminals of the first NPN bipolar transistor and the second NPN bipolar transistor are coupled to the third terminal, and the base terminals of the first NPN bipolar transistor and the second NPN bipolar transistor are coupled to the first node, wherein an emitter area of the second NPN bipolar transistor is greater than an emitter area of the first NPN bipolar transistor;
a third resistance coupled between the emitter terminal of the first NPN bipolar transistor and the second terminal, and a fourth resistance coupled between the emitter terminal of the second NPN bipolar transistor and the emitter terminal of the first NPN bipolar transistor;
and
a comparison circuit configured to determine whether a first current flowing through the collector terminal of the first NPN bipolar transistor is greater than a second current flowing through the collector terminal of the second NPN bipolar transistor, assert the comparison signal in response to determining that the first current is greater than the second current, and de-assert the comparison signal in response to determining that the first current is smaller than the second current.

4 more elements

Dependencies are inferred from the claim text.