Test circuit and memory device including thereof, and operation method of memory device
AssigneeSamsung Electronics Co., Ltd.
InventorJISOO LEE
Life of this patent
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Abstract
A test circuit connected to a program wordline and a read wordline of an anti-fuse memory device is provided. The test circuit includes: a first pulling circuit connected to a first pulling node, wherein the first pulling circuit is configured to electrically float the first pulling node based on a mode selection signal; a first test transistor connected between the first pulling node and a middle node, wherein a first gate terminal of the first test transistor is connected to the program wordline; a second test transistor connected between the middle node and a second pulling node, wherein a second gate terminal of the second test transistor is connected to the read wordline; and a second pulling circuit connected to the second pulling node.
Claims20
A test circuit connected to a program wordline and a read wordline of an anti-fuse memory device, the test circuit comprising:
- a first pulling circuit connected to a first pulling node, wherein the first pulling circuit is configured to electrically float the first pulling node based on a mode selection signal;
- a first test transistor connected between the first pulling node and a middle node, wherein a first gate terminal of the first test transistor is connected to the program wordline;
- a second test transistor connected between the middle node and a second pulling node, wherein a second gate terminal of the second test transistor is connected to the read wordline;
- and
- a second pulling circuit connected to the second pulling node.
A memory device comprising:
- a row decoder configured to control a first program wordline and a first read wordline;
- a memory cell array comprising a first anti-fuse memory cell row which is connected to the first program wordline and the first read wordline;
- and
- a test circuit comprising:
- a first test transistor comprising a first gate terminal connected to the first program wordline;
- and
- a second test transistor comprising a second gate terminal connected to the first read wordline,
- wherein the test circuit is configured to float a channel of the first test transistor during a first time period and a program operation is performed on the first anti-fuse memory cell row during the first time period.
An operation method of a memory device including a plurality of anti-fuse memory cells connected to a first program wordline, the operation method comprising:
- floating a channel of a first test transistor connected between a first node and a second node, wherein a first gate terminal of the first test transistor is connected to the first program wordline;
- and
- providing a program voltage to the first program wordline.
Dependencies are inferred from the claim text.