Memory device and method for operating thereof

A memory device comprising:

• a memory block including a first cell string and a second cell string having a faster erase speed than the first cell string;
• and
• a peripheral circuit configured to perform an erase operation on the memory block, the erase operation including an erase setting operation, an erase execution operation, and a discharge operation, which are sequentially performed,
• wherein the peripheral circuit is configured to perform the erase setting operation of the second cell string at a later time point than the erase setting operation of the first cell string.

A method of operating a memory device, the method comprising:

• adjusting, to a target level, a voltage of a first bit line connected to a first cell string, a voltage of a second bit line connected to a second cell string, and a voltage of a source line connected to the first and second cell strings, the second cell string having a faster erase speed than the first cell string;
• erasing data of the first and second cell strings;
• and
• discharging each of the first bit line, the second bit line, and the source line,
• wherein erasing the data includes erasing the data of the first cell string for a first time period and erasing the data of the second cell string for a second time period shorter than the first time period.