Rram device as physical unclonable function device and manufacturing method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChung-Liang CHENG
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Abstract
A resistive random access memory array includes a plurality of memory cells. Each memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element. The resistive random access memory array is used to generate physical unclonable function data.
Claims20
A method, comprising:
- forming a stack of first semiconductor nanostructures of a transistor;
- forming a stack of second semiconductor nanostructures;
- forming a first semiconductor structure coupled to the first semiconductor nanostructures and corresponding to a source/drain region of the transistor;
- depositing a first dielectric layer wrapped around the first semiconductor nanostructures corresponding to a gate dielectric of the transistor;
- depositing a second dielectric layer wrapped around the second semiconductor nanostructures;
- depositing a first metal structure wrapped around first semiconductor nanostructures and separated from the first semiconductor nanostructures by the first dielectric layer and corresponding to a gate electrode of the transistor;
- depositing a second metal structure wrapped around second semiconductor nanostructures and separated from the second semiconductor nanostructures by the second dielectric layer;
- replacing, after depositing the second metal structure, the second semiconductor nanostructures with a plurality of metal nanostructures, wherein the second dielectric layer and the second metal structure are wrapped around the plurality of metal nanostructures.
A method, comprising:
- forming a plurality of stacked channels of a transistor of a memory cell of a resistive random access memory array;
- forming a plurality of stacked metal nanostructures of a first electrode of a resistor device of the memory cell, wherein a top channel of the stacked channels is at a same vertical level as a top metal nanostructure of the stacked metal nanostructures;
- forming a resistive element of the resistor device wrapped around the stacked metal nanostructures;
- forming a second electrode of the resistor device wrapped around the metal nanostructures and separated form the metal nanostructures by the resistive element.
A method, comprising:
- forming a gate all around transistor of a resistive random access memory cell of an integrated circuit;
- and
- forming a resistor device of the resistive random access memory cell, including:
- forming a bottom electrode of the resistor device including a plurality of conductive nanosheets;
- forming a resistive element of the resistive random access memory cell at least partially surrounding the conductive nanosheets;
- and
- forming a top electrode of the resistor device separated from the conductive nanosheets by the resistive element and including a first void.
Dependencies are inferred from the claim text.