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US 2026/0171129 A1Published application
System and method for data reading in a multi-clock environment
AssigneeEM Microelectronic-Marin SA
InventorOvidiu SIMA
Life of this patent
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Abstract
A data reading system including two clock sources (CS1 and CS2), a configuration/access interface (C/A-I), and various logic and register modules. The system includes a configuration/access logic module (C/A-L) that receives signals from CS1 and interfaces with the data logic module (DL). The data register module (DR) stores data and provides it to a data output register module (DOR), which generates a data output signal. The system features a read window generator (RWG) and a read manager (RM) to manage reading operations. The system operates in an idle or reading state, controlling data flow based on the state of the configuration/access interface.
Claims6
A data reading system includes:
- a first clock source (CS1) and a second clock source (CS2), the first clock source being configured to provide a first clock source signal (cs1_signal) and the second clock source being configured to provide a second clock source signal (cs2_signal);
- a configuration/access interface (C/A-I);
- a configuration/access logic module (C/A-L) configured to receive the first clock source signal (cs1_signal) and connected to the configuration/access interface (C/A-I);
- a data logic module (DL) configured to receive the second clock source signal (cs2_signal) and connected the configuration/access logic module (C-A/L);
- a data register module (DR) configured to store a data, to receive the second clock source signal (cs2_signal), to generate a data signal (data) which represents the read data input, and to interact with the data logic module (DL);
- wherein the system further comprises:
- a data output register module (DOR) configured to store a data, said data output, to receive the data signal (data), and to generate a data output signal (data_output) which represents the read data output;
- a read window generator module (RWG) which is connected to the configuration/access logic module (C/A-L) and configured to generate a sample data signal (sample_data);
- a read manager module (RM) which is configured to receive the second clock source (CS2) and which is connected to the read window generator module (RWG);
- a read clock controller module (RCC) which is configured to receive the second clock source (CS2) and which is connected to the data output register module (DOR),
- wherein
- the configuration/access interface (C/A-I) presents a state corresponding to an idle state or a reading state;
- the configuration/access logic module (C/A-L) is configured to generate a read signal (read) on the sampling edge of first clock signal (cs1_signal) which represents the state of the configuration/access interface;
- the configuration/access interface logic module (C/A-L) is configured to receive the data output signal (data_output) on the next sampling edge of first clock signal (cs1_signal) after the read signal (read) has been set to ‘1’;
- the data output register module (DOR) being further configured to store the data received from the data signal (data) as its data output when the read signal corresponds to the idle state of the configuration/access interface (C/A-I).
12 more elements
A method for reading data, comprising the steps of:
- providing a first clock signal (cs1_signal) from a first clock source (CS1) and a second clock signal (cs2_signal) from a second clock source (CS2);
- receiving, by a configuration/access logic module (C/A-L), the first clock signal (cs1_signal) via a configuration/access interface (C/A-I);
- receiving, by a data logic module (DL), the second clock signal (cs2_signal) and interacting with the configuration/access logic module (C/A-L);
- storing data in a data register module (DR), receiving the second clock signal (cs2_signal), and generating a data signal (data) representing the data;
- wherein the method further comprises:
- storing data in a data output register module (DOR), receiving the data signal (data), and generating a data output signal (data_output) representing the stored data;
- generating a read window using a read window generator module (RWG), connected to the configuration/access logic module (C/A-L) and configured to generate a sample data signal (sample_data);
- managing the reading of data using a read manager module (RM), receiving the second clock signal (CS2) and interacting with the read window generator module (RWG), before the next sampling edge of first clock signal (cs1_signal);
- controlling the read clock using a read clock controller module (RCC), receiving the second clock signal (CS2) and interacting with the data output register module (DOR);
- determining a state of the configuration/access interface (C/A-I), the state corresponding to an idle state or a reading state;
- generating a read signal (read) representing the state of the configuration/access interface (C/A-I) via the configuration/access logic module (C/A-L);
- receiving the data output signal (data_output) by the configuration/access logic module (C/A-L);
- storing the data received from the data signal (data) as the data output in the data output register module (DOR) when the read signal corresponds to the idle state of the configuration/access interface (C/A-I).
10 more elements
Dependencies are inferred from the claim text.