Shift Register and Drive Method Therefor, Gate Drive Circuit, and Display Apparatus

A shift register, comprising:

• a shift sub-circuit and an output sub-circuit;
• wherein
• the shift sub-circuit is electrically connected with a signal input terminal, a first clock signal terminal, a second clock signal terminal, a first power supply terminal, a second power supply terminal, and a cascaded signal output terminal respectively, and is configured to provide a signal to the cascaded signal output terminal under control of signals of the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, and the second power supply terminal;
• the output sub-circuit is electrically connected with the shift sub-circuit, a latch signal terminal, a first control signal terminal, a second control signal terminal, a third power supply terminal, a fourth power supply terminal, a fifth power supply terminal, the cascaded signal output terminal, and a drive signal output terminal respectively, and is configured to provide a signal to the drive signal output terminal under control of signals of the shift sub-circuit, the latch signal terminal, the first control signal terminal, the second control signal terminal, the cascaded signal output terminal, the third power supply terminal, the fourth power supply terminal, and the fifth power supply terminal;
• the shift sub-circuit comprises:
• at least one shift output transistor, the shift output transistor is electrically connected with the cascaded signal output terminal, and the output sub-circuit comprises:
• at least one drive output transistor, and the drive output transistor is electrically connected with the drive signal output terminal;
• the shift sub-circuit further comprises:
• at least one transistor, and the output sub-circuit further comprises:
• at least one transistor;
• the shift sub-circuit is provided with a third node, a control electrode of the at least one drive output transistor is electrically connected with the third node through the at least one transistor of the output sub-circuit, and a control electrode of the at least one shift output transistor is electrically connected with the third node through the at least one transistor of the shift sub-circuit.