Information Synchronization Method and Apparatus

An information synchronization method, comprising:

• receiving a first request from a first processor, wherein the first request comprises a first memory address and first data and indicates to write the first data to the first memory address;
• writing, in response to the first request the first data to the first memory address according to a queuing sequence, wherein the queuing sequence is based on a data state at the first memory address and a capacity of the first memory address;
• receiving a second request from a second processor, wherein the second request comprises the first memory address and indicates to read target data from the first memory address;
• sending the target data in response to the second request;
• and
• reading, by the second processor, the target data.

An electronic device comprising:

• a bus;
• a transmitter;
• a plurality of processors operably coupled with the bus and comprising a first processor and a second processor;
• a memory operably coupled with the plurality of processors, the apparatus communicates with the processing units through the bus, the apparatus wherein the memory comprises a queue group, and wherein the queue group comprises a plurality of queues;
• and
• a receiver configured to receive a first request from the first processor, wherein the first request comprises a first memory address and first data and indicates to write the first data to a first queue of the plurality of queues and corresponding to the first memory address,
• wherein the plurality of processors is configured to:
• determine whether the queue group comprises the first queue corresponding to the first memory address;
• dynamically map the first memory address to an idle queue in the queue group to establish the first queue when the queue group does not comprise the first queue;
• and
• when the queue group comprises the first queue, write the first data to the first queue in response to the first request,
• wherein the receiver is further configured to receive a second request from the second processor, wherein the second request comprises the first memory address, and wherein the second request indicates to read target data from the first queue,
• wherein the transmitter is configured to send the target data to the bus only after the receiver receives the second request, wherein no large amount of invalid data is generated on the bus.