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US 2026/0169922 A1Published application
Reliability availability serviceability solutions for compute express link devices with reduced overprovisioning
AssigneeMicron Technology, Inc.
InventorsMarco Sforzin, Su Wei Lim
Life of this patent
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Abstract
Systems and methods are disclosed, including prefetching, by a memory controller of a memory system of the computing system, at least two cache lines as a combined cache line in response to a memory access request from a host system of the computing system; and performing, by the memory controller, reduced chip fail error recovery to detect errors on data of the combined cache line.
Claims20
A memory system comprising:
- a memory array including memory cells that are included in multiple memory dies;
- and
- a memory controller operatively coupled to the memory dies and including at least one of:
- controller processing circuitry configured to prefetch at least two cache lines as a combined cache line in response to a memory access request;
- and
- error recovery circuitry configured to provide less than full data recovery from a chip fail event.
3 more elements
A method of operating a computing system, the method comprising:
- prefetching, by a memory controller of a memory system of the computing system, at least two cache lines as a combined cache line in response to a memory access request from a host system of the computing system;
- and
- performing, by the memory controller, reduced chip fail error recovery to detect errors on data of the combined cache line.
A computing system comprising:
- a memory system including a memory array including memory cells that are included in multiple memory dies, and a memory controller operatively coupled to the memory dies;
- and
- a host system including host processing circuitry configured to send a memory request to the memory system;
- and
- wherein the memory controller includes:
- controller processing circuitry configured to prefetch at least two cache lines as a combined cache line in response to a memory access request;
- and
- error recovery circuitry configured to provide reduced chip fail error recovery on the combined cache line.
5 more elements
Dependencies are inferred from the claim text.