US 2026/0169871 A1 · ENCODING SCHEMES FOR REDUNDANT SYSTEMS

Abstract

An apparatus comprising a plurality of processors coupled with a plurality of interconnects, e.g., sets of principle and redundant interconnects, to transmit/receive signals between the plurality of processors using one or more encoding schemes (e.g., first and second encoding schemes) based on an indication associated with the plurality of processors. The indication may manifest as a change in logic levels, e.g., first and second logic levels, where the first and second logic levels are different. The first encoding scheme signals over some but not all the sets of redundant interconnects based on the indication being the first logic level. The second encoding scheme signals over the set of principle interconnects and the set of redundant interconnects based on the indication being the second logic level, wherein the second encoding scheme is a one-hot encoding scheme.

Claims25

Dependent claims

An apparatus comprising:

a plurality of processors including a first processor and a second processor;
and
a plurality of interconnects coupled to the plurality of processors, wherein the plurality of interconnects further includes a plurality of principle interconnects and a plurality of redundant interconnects, wherein the plurality of interconnects is to transmit signals between the first processor and the second processor using one or more encoding schemes based on an indication from one or more logics associated with the plurality of processors, wherein the one or more encoding schemes includes a first encoding scheme and a second encoding scheme, wherein the first encoding scheme applies signals over some but not all of the plurality of redundant interconnects based on a first logic level of the indication, and wherein the second encoding scheme applies signals over the plurality of principle interconnects and the plurality of redundant interconnects based on a second logic level of the indication, and wherein the first logic level is different from the second logic level.

A wafer-level assembly of chiplets comprising:

a plurality of groups of chiplets including a first group of chiplets, and a second group of chiplets, wherein the first group of chiplets is organized as a first fully-connected configuration, and wherein the second group of chiplets is organized as a second fully-connected configuration;
and
a plurality of interconnects including a first set of interconnects and a second set of interconnects, wherein the first set of interconnects couples a first chiplet of the first group of chiplets with a first chiplet of the second group of chiplets, wherein the second set of interconnects couples a second chiplet of the first group of chiplets with a second chiplet of the second group of chiplets, wherein the plurality of interconnects is arranged in a mesh configuration, wherein the first set of interconnects includes a first set of principle interconnects and a first set of redundant interconnects, wherein the second set of interconnects includes a second set of principle interconnects and a second set of redundant interconnects,
wherein the plurality of interconnects is to transmit signals between the first chiplet of the first group of chiplets and the first chiplet of the second group of chiplets using one or more encoding schemes based on an indication from one or more logics associated with the plurality of groups of chiplets, wherein the one or more encoding schemes includes a first encoding scheme and a second encoding scheme, wherein the first encoding scheme applies signals over some but not all of the first and second sets of redundant interconnects based on a first logic level of the indication, and wherein the second encoding scheme applies signals over the first and second sets of principle interconnects and the first and second sets of redundant interconnects based on a second logic level of the indication, and wherein the first logic level is different from the second logic level.

1 more element

A wafer-level assembly of chiplets comprising:

a plurality of groups of chiplets including a first group of chiplets, a second group of chiplets, wherein the first group of chiplets is organized as a first fat-tree configuration, and wherein the second group of chiplets is organized as a second fat-tree configuration;
and
a plurality of interconnects including a first set of interconnects and a second set of interconnects, wherein the first set of interconnects couples a first chiplet of the first group of chiplets with a first chiplet of the second group of chiplets, wherein the second set of interconnects couples a second chiplet of the first group of chiplets with a second chiplet of the second group of chiplets, wherein the plurality of interconnects is arranged in a mesh configuration, wherein the first set of interconnects includes a first set of principle interconnects and a first set of redundant interconnects, wherein the second set of interconnects includes a second set of principle interconnects and a second set of redundant interconnects,
wherein the plurality of interconnects is to transmit signals between the first chiplet of the first group of chiplets and the first chiplet of the second group of chiplets using one or more encoding schemes based on an indication from one or more logics associated with the plurality of groups of chiplets, wherein the one or more encoding schemes includes a first encoding scheme and a second encoding scheme, wherein the first encoding scheme applies signals over some but not all of the first and second sets of redundant interconnects based on a first logic level of the indication, and wherein the second encoding scheme applies signals over the first and second sets of principle interconnects and the first and second sets of redundant interconnects based on a second logic level of the indication, and wherein the first logic level is different from the second logic level.

1 more element

Dependencies are inferred from the claim text.

Encoding schemes for redundant systems

Life of this patent

Encoding schemes for redundant systems

Life of this patent

Abstract

Claims25