Processors, methods, and systems to perform immediate folding for logical registers having different widths

A method comprising:

• decoding a first instruction, decoding a second instruction after the first instruction, and decoding a third instruction after the second instruction, the first instruction specifying a source register, a first immediate, and a destination register, the second instruction specifying the destination register of the first instruction as a source register, a second immediate, and a destination register, the third instruction specifying the destination register of the second instruction as a source register;
• and
• when an operand size of the second instruction is wider than an operand size of the first instruction, performing operations associated with the third instruction, including:
• generating a second value from a first value obtained from a physical register that the destination register of the second instruction is mapped to via register renaming, including truncating bits of the first value more significant than the operand size of the first instruction;
• and
• generating a value of the destination register of the second instruction, including combining the second value with an accumulated immediate incorporating at least the first immediate and the second immediate.

A system comprising:

• a dynamic random access memory (DRAM);
• and
• a processor coupled with the DRAM, the processor to:
• decode a first instruction, a second instruction after the first instruction, and a third instruction after the second instruction, the first instruction to specify a source register, a first immediate, and a destination register, the second instruction to specify the destination register of the first instruction as a source register, a second immediate, and a destination register, the third instruction to specify the destination register of the second instruction as a source register;
• and
• perform operations associated with the third instruction, including, when an operand size of the second instruction is wider than an operand size of the first instruction, to:
• generate a second value from a first value obtained from a physical register that the destination register of the second instruction is mapped to via register renaming, including to truncate bits of the first value more significant than the operand size of the first instruction;
• and
• generate a value of the destination register of the second instruction, including to combine the second value with an accumulated immediate incorporating at least the first immediate and the second immediate.