Shadow stack management with micro-operations

A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a processor core, wherein the processor core is coupled to a memory hierarchy, and wherein the processor core is configured to execute shadow stack operations and micro-operations;
• decoding a shadow stack operation, wherein the shadow stack operation is associated with a shadow stack pointer (SSP), and wherein the shadow stack operation is associated with an implementation mode;
• substituting the shadow stack operation with at least two micro-operations, wherein the substituting is based on the implementation mode;
• and
• executing the at least two micro-operations.

A computer system for instruction execution comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a processor core, wherein the processor core is coupled to a memory hierarchy, and wherein the processor core is configured to execute shadow stack operations and micro-operations;
• decode a shadow stack operation, wherein the shadow stack operation is associated with a shadow stack pointer (SSP), and wherein the shadow stack operation is associated with an implementation mode;
• substitute the shadow stack operation with at least two micro-operations, wherein the substituting is based on the implementation mode;
• and
• execute the at least two micro-operations.