Vector-integer store data avoidance scheme

A method to share data lines between vector and integer operations comprising:

• scheduling a dispatch of a vector store data operation to transfer vector data to a destination;
• blocking dispatch of an integer store data operation to the destination;
• routing lower bits of the vector data to a first set of connection lines used for routing of integer data to the destination and using the first set of connection lines to route the lower bits of the vector data to the destination;
• and
• routing higher bits of the vector data via a second set of connection lines to a destination.

A system comprising:

• a memory;
• a switch coupled to the memory;
• a cluster of integer units, each integer unit having an integer logic circuit to dispatch an integer store data operation to route integer data to the switch on a first set of connection lines, wherein the switch switches corresponding one of the first set of connection lines onto a third set of connection lines to the memory;
• and
• a cluster of vector units, each vector unit having a vector logic circuit to schedule a vector store data operation to transfer vector data to the memory, block dispatch of an integer store data operation to the memory, route higher bits of the vector data via a second set of connection lines to the memory, and route lower bits of the vector data to a corresponding integer logic circuit and use the first set of connection lines used for routing of integer data to the switch, wherein the switch to route the lower bits of the vector data to the memory on the third set of connection lines.