Test device for performing test on combinational logic circuit, and method of operating the test device
AssigneeSamsung Electronics Co., Ltd.
InventorsJeongmin LEE, Jung-Ho SONG
Life of this patent
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AssigneeSamsung Electronics Co., Ltd.
InventorsJeongmin LEE, Jung-Ho SONG
Estimating the term…
A test device for testing a combinational logic circuit configured to be in electrical communication with an analog circuit includes a plurality of flip-flops, each of which is connected to the combinational logic circuit; and one or more processors connected to the plurality of flip-flops and configured to test the combinational logic circuit based on a scan signal. The one or more processors are configured to: input an input pattern to the combinational logic circuit through the plurality of flip-flops; obtain a first output value output from a first output node of the combinational logic circuit; determine whether a short current occurs in the analog circuit, by inputting the first output value into the analog circuit; and connect a first cell circuit corresponding to the first output value between the first output node and the analog circuit based on a determination that the short current does not occur.
A test device for testing a combinational logic circuit configured to be in electrical communication with an analog circuit, the test device comprising:
A method of operating a test device for performing a scan test on a combinational logic circuit configured to be in electrical communication with an analog circuit, the method comprising:
An integrated circuit comprising:
Dependencies are inferred from the claim text.