Semiconductor package

A method of fabricating a semiconductor package, the method comprising:

• forming a substrate including substrate pads, wherein the substrate pads include a first substrate pad and a second substrate pad alternately disposed from a plan view;
• arranging a first upper semiconductor chip on the substrate, wherein the first upper semiconductor chip includes a first conductive chip pad and a second conductive chip pad alternately arranged on a top surface thereof in the plan view;
• forming a first upper bonding wire connecting the first conductive chip pad and the first substrate pad;
• and
• forming a second upper bonding wire connecting the second conductive chip pad and the second substrate pad,
• wherein the substrate further includes
• a first region between the first and second conductive chip pads and the substrate pads, and
• a second region between the first region and the substrate pads,
• wherein the second upper bonding wire has a highest vertical level on the first region of the substrate,
• wherein the first upper bonding wire is provided at a higher vertical level than the second upper bonding wire on the first region of the substrate, and
• wherein the second upper bonding wire is provided at a higher vertical level than the first upper bonding wire on the second region of the substrate.

A method of manufacturing a semiconductor package, the method comprising:

• forming a substrate, wherein the substrate includes a first substrate pad, a second substrate pad, and a third substrate pad provided on a top surface of the substrate;
• disposing a lower semiconductor chip on the top surface of the substrate;
• disposing a first upper semiconductor chip on a top surface of the lower semiconductor chip, wherein the first upper semiconductor chip includes a first conductive chip pad and a second conductive chip pad placed adjacent to each other on a top surface of the first upper semiconductor chip;
• forming lower bonding wires connecting the lower semiconductor chip and the substrate;
• forming a first upper bonding wire connecting the first conductive chip pad and the first substrate pad;
• forming a second upper bonding wire connecting the second conductive chip pad and the second substrate pad;
• and
• forming a molding layer on the top surface of the substrate,
• wherein the molding layer covers the lower semiconductor chip, the first upper semiconductor chip, the lower bonding wires, the first upper bonding wire, and the second upper bonding wire,
• wherein, when viewed in plan, the substrate further includes
• a first region between the first conductive chip pad and the first substrate pad and between the second conductive chip pad and the second substrate pad, and
• a second region between the first region and the first and second substrate pads,
• wherein, on the second region of the substrate, a vertical level difference between adjacent lower bonding wires is less than a vertical level difference between the second upper bonding wire and the first upper bonding wire.