Mask, integrated circuit, and method of controlling threshold voltages of the integrated circuit by using the mask

An integrated circuit comprising:

• a plurality of logic cell regions where a plurality of respective logic cells are formed;
• a first switch cell region disposed adjacent to a first logic cell region of the plurality of logic cell regions;
• a plurality of power rails extending in a first horizontal direction, formed in the plurality of logic cell regions and the first switch cell region, and configured to be supplied with a source voltage;
• a plurality of first gate structures disposed apart from each other in the first horizontal direction in one logic cell region selected from among the plurality of logic cell regions and extending in a second horizontal direction intersecting with the first horizontal direction;
• and
• a plurality of second gate structures disposed apart from each other in the first horizontal direction in the switch cell region and extending in the second horizontal direction,
• wherein the switch cell region is electrically isolated from each of the plurality of logic cell regions, and
• the plurality of first gate structures and the plurality of second gate structures result in transistors controlled by the first gate structures having different threshold voltages from transistors controlled by the second gate structures.

A method of controlling threshold voltages for a plurality of transistors of a device to be manufactured, the device to be manufactured including a plurality of logic cell regions in which a logic cell is formed, an active cell region in which an active cell is formed, and a first dummy cell region adjacent to a first logic cell region of the plurality of logic cell regions and adjacent to the active cell region, the first dummy cell region including a break region electrically isolated from each of the plurality of logic cell regions, the logic cell having a first width in a first direction and the active cell having a second width smaller than the first width in the first direction, the first dummy cell region being adjacent to the active cell region in the first direction, the method including:

• placing a device under manufacture that is to be formed into the device to be manufactured in a process chamber, the device under manufacture having device regions that correspond to the regions of the device to be manufactured;
• performing a first doping process on the device under manufacture by using a first mask that includes an opening exposing the device region corresponding to the active cell, exposing the device region corresponding to the first dummy cell region, and exposing the device region corresponding to the first logic cell region;
• and
• performing a second doping process on the device under manufacture by using a second mask that includes an opening exposing the device region corresponding to the active cell, exposing the device region corresponding to the first dummy cell region, and covering the device region corresponding to the first logic cell region.