Method for making single-photon avalanche diode (spad) devices including a superlattice at multiplication region interface

A method for making a single-photon avalanche diode (SPAD) device comprising:

• forming a deep well region in a semiconductor substrate having a first conductivity type, the deep well region having a second conductivity type different than the first conductivity type;
• forming a multiplication region in the deep well region having the second conductivity type;
• forming a central active region on the multiplication region and having the first conductivity type;
• forming a guard ring surrounding the central active region and the multiplication region and having the first conductivity type;
• forming a plurality of contact regions adjacent the guard ring;
• and
• forming a superlattice layer adjacent at an interface between the multiplication region and the central active region, the superlattice layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A method for making a single-photon avalanche diode (SPAD) device comprising:

• forming a deep well region in a semiconductor substrate having a first conductivity type, the deep well region having a second conductivity type different than the first conductivity type;
• forming a multiplication region in the deep well region having the second conductivity type;
• forming a central active region on the multiplication region and having the first conductivity type;
• forming a guard ring surrounding the central active region and the multiplication region and having the first conductivity type;
• and
• forming a superlattice layer adjacent an interface between the multiplication region and the central active region, the superlattice layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.