High voltage semiconductor device and manufacturing method of high voltage semiconductor device

A method of manufacturing a semiconductor device comprising a first device and a second device on a substrate, the method comprising:

• implanting N-type dopants on the substrate to form a first N-type buried layer (NBL) in the first device and a second NBL in the second device;
• forming an epitaxial layer on the first and second NBLs;
• forming an N-type deep well (DNW) region on the first NBL and a P-type deep well (DPW) region on the second NBL;
• forming a P-type buried layer (PBL) in the DPW region;
• forming a P-type drift region in the DNW region and an N-type drift region in the DPW region;
• forming a first gate electrode on the DNW and a second gate electrode on the DPW;
• forming an N-type body region in the DNW region and a P-type body region in the DPW region;
• forming a P-type source region in the N-type body region and a P-type drain region in the P-type drift region;
• forming an N-type source region in the P-type body region and an N-type drain region in the N-type drift region;
• forming a first non-silicide layer between the first gate electrode and the P-type drain region in the first device;
• and
• forming a second non-silicide layer between the second gate electrode and the N-type drain region in the second device, the first and second non-silicide layers being insulative.