Metal-oxide-silicon (mos) varactor and method of forming
AssigneeMicrochip Technology Incorporated
InventorYaojian Leng
Life of this patent
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Abstract
An integrated circuit apparatus includes a transistor and a varactor. The transistor includes a transistor source and a transistor drain formed in a transistor well area of a semiconductor substrate, a transistor gate oxide formed over the substrate, and a transistor gate formed over the transistor gate oxide. The varactor is located laterally offset from the transistor and includes a pair of varactor source/drain regions formed in a varactor well area of the semiconductor substrate, a varactor gate insulator formed over the substrate, and a varactor gate formed over the varactor gate insulator, wherein the varactor gate is formed from a different material than the transistor gate.
Claims20
An integrated circuit device, comprising:
- a transistor comprising:
- a transistor source and a transistor drain formed in a transistor well area of a semiconductor substrate;
- a transistor gate oxide formed over the substrate;
- and
- a transistor gate formed over the transistor gate oxide;
- and
- a varactor laterally offset from the transistor, the varactor comprising:
- a pair of varactor source/drain regions formed in a varactor well area of the semiconductor substrate;
- a varactor gate insulator formed over the substrate;
- and
- a varactor gate formed over the varactor gate insulator, wherein the varactor gate is formed from a different material than the transistor gate.
A method of forming a varactor, comprising:
- forming a pair of varactor source/drain regions in a varactor well area of a semiconductor substrate;
- forming a dielectric region over the semiconductor substrate;
- performing a first etch to form a tub opening and a pair of varactor source/drain contact openings in the dielectric region;
- depositing a contact metal over the dielectric region and extending into the tub opening and into the pair of varactor source/drain contact openings;
- performing a second etch to remove the contact metal in the tub opening;
- depositing a varactor gate insulator layer over the dielectric region and extending down into the tub opening;
- depositing a varactor gate metal layer over the varactor gate insulator layer and extending down into the tub opening;
- and
- performing a planarization process to remove upper portions of the varactor gate metal layer and upper portions of the varactor gate insulator layer;
- wherein after the planarization process, a remaining portion of the varactor gate insulator layer defines a cup-shaped varactor gate insulator, a remaining portion of the varactor gate metal layer defines a varactor gate in an opening defined by the cup-shaped varactor gate insulator, and remaining portions of the contact metal in the pair of varactor source/drain contact openings defines a pair of varactor source/drain contacts.
A method of forming an integrated circuit device, comprising:
- forming (a) a pair of transistor source/drain regions in a transistor well area of a semiconductor substrate and (b) a pair of varactor source/drain regions in a varactor well area of the semiconductor substrate;
- forming a transistor gate oxide over the transistor well area;
- forming a transistor gate over the transistor gate oxide;
- forming a dielectric region over the semiconductor substrate and over the transistor gate;
- etching the dielectric region to form a tub opening over the varactor well area, and a pair of varactor source/drain contact openings over the pair of varactor source/drain regions, respectively;
- depositing a contact metal over the dielectric region and extending into the tub opening and into the pair of varactor source/drain contact openings;
- performing an etch to remove the contact metal from the tub opening;
- depositing a varactor gate insulator layer over the dielectric region and extending down into the tub opening;
- depositing a varactor gate metal layer over the varactor gate insulator layer and extending down into the tub opening;
- and
- performing a planarization process to remove upper portions of the varactor gate metal layer and upper portions of the varactor gate insulator layer;
- wherein after the planarization process, a remaining portion of the varactor gate insulator layer defines a cup-shaped varactor gate insulator, a remaining portion of the varactor gate metal layer defines a varactor gate in an opening defined by the cup-shaped varactor gate insulator, and remaining portions of the contact metal in the pair of varactor source/drain contact openings defines a pair of varactor source/drain contacts.
Dependencies are inferred from the claim text.