3d memory device and method of implementing multi-level memory using the same

Abstract

A 3D memory device may include a plurality of memory cells arranged in three dimensions on a substrate. Each of the plurality of memory cells may include a transistor and a plurality of self-selecting memory layers connected to the transistor. The transistor may include at least one channel layer parallel to the substrate. Each of the plurality of self-selecting memory layers may include a chalcogenide-based material having Ovonic threshold switching characteristics. A threshold voltage of the chalcogenide-based material may change according to a polarity and an intensity of an applied voltage. The plurality of self-selecting memory layers may be configured to have different threshold voltages from each other, so that each of the plurality of memory cells may implement a multilevel memory.

Dependencies are inferred from the claim text.