Semiconductor device including resistive memory cell and cell control transistor connected to resistive memory cell
AssigneeSK hynix Inc.
InventorJae Yeon LEE
Life of this patent
Estimating the term…
Abstract
A semiconductor device according to an embodiment includes a cell control transistor, a resistive memory cell, and a bit line that are disposed on a substrate and coupled to one another. The resistive memory cell includes a cell selection transistor disposed to be spaced apart from the cell control transistor on the substrate, and a variable resistance element electrically connected to a drain electrode of the cell selection transistor. A source electrode of the cell control transistor and a source electrode of the cell selection transistor are electrically connected to the bit line in common.
Claims20
A semiconductor device comprising:
- a cell control transistor, a resistive memory cell, and a bit line that are disposed on a substrate and coupled to one another,
- wherein the resistive memory cell comprises:
- a cell selection transistor disposed to be spaced apart from the cell control transistor on the substrate;
- and
- a variable resistance element electrically connected to a drain electrode of the cell selection transistor, and
- wherein a source electrode of the cell control transistor and a source electrode of the cell selection transistor are electrically connected to the bit line in common.
A semiconductor device comprising:
- a cell control transistor and a plurality of resistive memory cells that share a bit line;
- wherein the cell control transistor comprises a control source region and a control drain region that are disposed in a substrate, and a control gate electrode layer disposed on the substrate between the control source region and the control drain region,
- wherein each of the plurality of resistive memory cells comprises:
- a cell selection transistor including a cell source region and a cell drain region that are disposed in the substrate, and a cell gate electrode layer disposed on the substrate between the cell source region and the cell drain region;
- and
- a variable resistance structure electrically connected to the cell drain region of the cell selection transistor, and
- wherein the control source region and the cell source region are electrically connected to the bit line in common.
Dependencies are inferred from the claim text.