Semiconductor device including active pattern and gate electrode

A semiconductor device, comprising:

• a memory cell array region and an interface region adjacent to each other in a first horizontal direction;
• active patterns including cell active patterns disposed within the memory cell array region and dummy active patterns disposed within the interface region;
• gate electrodes traversing the memory cell array region and extending into the interface region;
• and
• conductive patterns traversing the memory cell array region and extending into the interface region,
• wherein at least a portion of each of the conductive patterns is disposed at a different level from the gate electrodes, wherein the cell active patterns include a first cell active pattern and a second cell active pattern adjacent to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein the gate electrodes include a first gate electrode and a second gate electrode passing between the first and second cell active patterns and spaced apart from each other, and wherein the conductive patterns include a first conductive pattern passing between the first cell active pattern and the second cell active pattern.

A semiconductor device, comprising:

• a memory cell array region and an interface region adjacent to each other in a first horizontal direction;
• active patterns including cell active patterns disposed in the memory cell array region and dummy active patterns disposed in the interface region;
• gate electrodes traversing the memory cell array region and extending into the interface region;
• first conductive patterns traversing the memory cell array region and extending into the interface region;
• bit lines extending in a second horizontal direction perpendicular to the first horizontal direction, connected to the cell active patterns, and disposed below the cell active patterns;
• data storage structures on the cell active patterns;
• and
• a contact structure between the cell active patterns and the data storage structure,
• wherein at least a portion of each of the first conductive patterns is at a different level from the gate electrodes, wherein the cell active patterns include a first cell active pattern and a second cell active pattern adjacent to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein the gate electrodes include a first gate electrode and a second gate electrode passing between the first and second cell active patterns and spaced apart from each other, and wherein one of the first conductive patterns passes between the first cell active pattern and the second cell active pattern.