Semi-Additive Process for Printed Circuit Boards

A process for forming a multi-layer circuit board having an inner core and one or more outer layers, the process comprising:

• forming said inner core on an inner core catalytic dielectric, the inner core catalytic dielectric containing catalytic particles which are exposed when the catalytic dielectric is drilled, the catalytic dielectric also having a thin top foil applied to a top surface of the inner core catalytic dielectric and a thin bottom foil applied to a bottom surface opposite the inner core catalytic dielectric top surface, the thin bottom foil overlaid with a removable backing foil which is thicker than the thin bottom foil:
• laser drilling at least one via through the thin top foil, the catalytic dielectric, the at least one via reaching the thin bottom foil without penetrating the thin bottom foil;
• removing the removable backing foil;
• optionally drilling at least one through hole extending through the top foil, the catalytic dielectric and the thin bottom foil;
• said laser drilled via and optional drilled thru hole having inner surfaces with exposed catalytic particles from drilling;
• electroless plating the exposed catalytic particles, said thin top copper foil, and said thin bottom copper foil;
• applying patterned resist to create exposed copper areas and concealed copper areas of the thin top copper foil and thin bottom copper foil;
• electroplating said exposed copper areas;
• tin plating said exposed copper areas;
• stripping said patterned resist;
• quick etching the inner core until the previously concealed copper areas are etched free of copper;
• thereby forming the inner core having a top surface and a bottom surface;
• each said outer layer formed by sequentially:
• applying a catalytic dielectric layer to an outer surface of the inner core or a previously applied outer layer, each catalytic dielectric layer also having a thin outer surface foil having at least one laser-drilled via or at least one thru hole through the outer layer to an underlying copper layer exposing catalytic particles;
• electroless plating the thin copper foil and the exposed catalytic particles;
• applying patterned resist to an exposed surface;
• electroplating the exposed surface to create an electroplated area;
• plating tin onto the electroplated area;
• stripping the patterned resist to expose electroless copper;
• quick etching the exposed electroless copper.

A process for forming a multi-layer circuit board having an inner core and one or more outer layers, the process comprising:

• on an inner core catalytic dielectric containing catalytic particles which are exposed when the catalytic dielectric is drilled, the inner core catalytic dielectric having a thin top foil on a top surface of the inner core catalytic dielectric and a thin bottom foil on a bottom surface opposite the inner core catalytic dielectric top surface, the thin bottom foil overlaid with a removable backing foil which is thicker than the thin bottom foil:
• laser drilling at least one via through the thin top foil, the inner core catalytic dielectric, the at least one via reaching the thin bottom foil without penetrating the thin bottom foil;
• removing the removable backing foil;
• optionally drilling at least one through hole extending through the top foil, through the catalytic dielectric and through the thin bottom foil;
• said laser drilled via and optional drilled thru hole having inner surfaces with catalytic particles exposed from drilling;
• electroless plating the exposed catalytic particles, said thin top copper foil, and said thin bottom copper foil;
• applying patterned resist to create exposed copper areas and concealed copper areas of the thin top copper foil and thin bottom copper foil;
• electroplating said exposed copper areas;
• tin plating said exposed copper areas;
• stripping said patterned resist;
• quick etching the inner core until the previously concealed copper areas are etched free of copper;
• thereby forming the inner core having a top surface and a bottom surface;
• each of said outer layers formed by:
• applying a catalytic dielectric layer a surface of the inner core, each catalytic dielectric layer also having a thin outer surface foil;
• laser drilling at least one via and one or more optional thru holes through the catalytic dielectric layer to an underlying copper layer, thereby also exposing catalytic particles;
• electroless plating the exposed thin copper foil and exposed catalytic particles;
• applying patterned resist to an exposed surface of the catalytic dielectric layer;
• electroplating the exposed surface;
• plating tin onto the electroplated areas;
• stripping the patterned resist;
• quick etching the exposed copper.

A process for making a multi-layer circuit board, the process comprising:

• forming a catalytic inner core;
• applying a succession of patterned catalytic outer layers, each patterned catalytic outer layer comprising a catalytic dielectric and a thin outer foil;
• where the catalytic inner core is a catalytic dielectric containing catalytic particles which are exposed when the catalytic dielectric is drilled, the catalytic dielectric having a thin top foil on a top surface of the inner core catalytic dielectric and a thin bottom foil on a bottom surface opposite the inner core catalytic dielectric top surface, the thin bottom foil overlaid with a removable backing foil which is thicker than the thin bottom foil, thereafter laser drilling at least one via through the thin top foil, the catalytic dielectric inner core, the at least one laser drilled via reaching the thin bottom foil without penetrating the thin bottom foil, thereafter removing the removable backing foil, thereafter optionally drilling at least one through hole extending through the top foil, the catalytic dielectric and the thin bottom foil, the laser drilled via and optional drilled thru hole having inner surfaces with exposed catalytic particles from drilling, thereafter electroless plating the exposed catalytic particles, said thin top copper foil, and said thin bottom copper foil, thereafter applying patterned resist to create exposed copper areas and concealed copper areas of the thin top copper foil and thin bottom copper foil, thereafter electroplating said exposed copper areas, thereafter tin plating said exposed copper areas, thereafter stripping said patterned resist, thereafter quick etching the inner core until the previously concealed copper areas are etched free of copper, the catalytic inner core thereby having a top surface and a bottom surface;
• each of the patterned catalytic outer layers formed by applying a catalytic dielectric layer to the top surface or the bottom surface of the inner core or a catalytic outer layer, each catalytic dielectric layer also having a thin outer surface foil, thereafter laser drilling at least one via and one or more optional thru holes through the outer layer to an underlying copper layer, thereafter laser drilling at least one via and one or more optional thru holes through a catalytic dielectric outer layer to an underlying copper layer, the laser drilled holes exposing catalytic particles of an associated catalytic dielectric layer, thereafter electroless plating the exposed thin copper foil and exposed catalytic particles, thereafter applying patterned resist to, thereafter electroplating exposed surfaces not covered by the patterned resist, thereafter plating tin onto the electroplated areas, thereafter stripping the patterned resist, thereafter quick etching the exposed copper.