Timing critical control circuit
AssigneeSkyworks Solutions, Inc.
InventorsSreedhar Vineel Reddy Kaipu, Shao-Min Hsu, Daniel Chang, Yeung Bun Choi, James Henry Ross, Bryan J. Roll, Sener Yuki Yalcin
Life of this patent
Estimating the term…
Abstract
A method for sending timing-critical instructions in a system, including transmitting a plurality of bits to a device having a switching controller, the plurality of bits being divided into a first set and a second set, by transmitting the first set during one or more first clock cycles, pausing for a period of time after transmitting the first set, and transmitting the second set during one or more second clock cycles.
Claims20
A method for sending timing-critical instructions in a system, comprising:
- transmitting a plurality of bits to a device having a switching controller, the plurality of bits being divided into a first set and a second set, by
- transmitting the first set during one or more first clock cycles,
- pausing for a period of time after transmitting the first set, and
- transmitting the second set during one or more second clock cycles.
A telecommunication system comprising:
- a transmitter configured to transmit outgoing signals;
- a receiver configured to receive inbound signals;
- one or more switches for routing inbound signals to one or mor first circuit elements and outgoing signals from one or more second circuit elements;
- and
- a controller configured to
- send one or more control signals to the one or more switches, the one or more control signals controlling the one or more switches to change states between transmitting and receiving states at high frequencies.
A non-transitory computer-readable medium containing thereon instructions for managing timing-critical instructions, the instructions instructing at least one processor to:
- transmit a plurality of bits to a device having a switching controller, the plurality of bits being divided into a first set and a second set, by
- transmit the first set during one or more first clock cycles,
- perform a pause after transmitting the first set, and
- transmit the second set during one or more second clock cycles;
- wherein the first set contains timing-critical instructions for the device;
- wherein the first set and the second set are exclusive sets of bits;
- wherein the device is a switching device;
- and
- transmitting each respective bit of the first set occurs during a respective clock cycle of the one or more first clock cycles, transmitting each respective bit of the second set occurs during a respective clock cycle of the one or more second clock cycles, and one or more timing-critical instructions corresponding to the first set are executed by the device during the pause.
Dependencies are inferred from the claim text.