Transmitter and receiver adopting correlated signaling for compensating for inter-channel mismatch and integrated circuit including the same
AssigneeUIF (University Industry Foundation), Yonsei University
InventorsKwanseo PARK, Sinho LEE
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Abstract
Provided is a transmitter adopting correlated signaling. The transmitter includes serializers and a phase interpolator configured to select a reference phase of a clock as any one of 0°, 90°, 180°, and 270° using a first code, fine-tune the selected reference phase by adding a phase selected using a second code thereto, and generate differential clocks using the fine-tuned reference phase, in which the phase selected using the second code is any one of 0°to 90°, and the differential clocks are used as synchronization clocks of each of the serializers.
Claims19
A transmitter comprising:
- a plurality of serializers;
- and
- a phase interpolator configured to select a reference phase of a clock as one of 0°, 90°, 180°, and 270° using a first code, fine-tune the selected reference phase by adding a phase selected using a second code thereto, and generate differential clocks using the fine-tuned reference phase,
- wherein the phase selected using the second code is one of 0° to 90°,
- wherein the differential clocks are synchronization clocks of each of the plurality of serializers.
A receiver comprising:
- a continuous time linear equalizer configured to receive a first channel signal input through a first channel and a second channel signal input through a second channel;
- a current mode amplifier configured to buffer output signals of the continuous time linear equalizer;
- a phase interpolator configured to select a reference phase of a clock as one of 0°, 90°, 180°, and 270° using a first code, fine-tune the selected reference phase by adding a selected phase using a second code thereto, and generate differential clocks using the fine-tuned reference phase;
- a first comparator configured to compare an output signal of the current mode amplifier with a first reference voltage using the differential clocks and output first bits;
- and
- a second comparator configured to compare the output signal of the current mode amplifier with a second reference voltage using the differential clocks and output second bits.
An integrated circuit comprising:
- a first transmitter;
- a second transmitter having the same structure as the first transmitter;
- a receiver;
- a first communication channel connected between a first output terminal of the first transmitter and a first input terminal of the receiver;
- and
- a second communication channel connected between a second output terminal of the second transmitter and a second input terminal of the receiver,
- wherein the first transmitter including:
- a plurality of serializers, and
- a phase interpolator configured to select a reference phase of a clock as one of 0°, 90°, 180°, and 270° using a first code, fine-tune the selected reference phase by adding a phase selected using a second code thereto, and generate differential clocks using the fine-tuned reference phase,
- wherein the phase selected using the second code is any one of 0° to 90°, and
- wherein the differential clocks are synchronization clocks of each of the plurality of serializers.
Dependencies are inferred from the claim text.