Priori bit pattern indexed error counts for accelerated link equalization training

A communication link device comprising:

• one or more processing devices operatively coupled to a second communication link device via a data channel, wherein the one or more processing devices are to:
• cause data to be received over the data channel from the second communication link device, wherein the data comprises known multi-bit patterns;
• sweep the data over voltage and time to generate eye diagram data;
• detect errors at identified cursors of the eye diagram data, wherein each identified cursor corresponds to a known multi-bit pattern within a set of previously transmitted bits;
• buffer counts of each detected error associated with a respective known multi-bit pattern of the set of previously transmitted bits;
• and
• determine, using the buffered counts, a plurality of decision feedback equalizer (DFE) coefficients to be employed in receiving unknown data over the data channel.

A method comprising:

• causing, by a processing device, data to be received over a memory channel from a memory device of a memory sub-system, wherein the data comprises known multi-bit patterns;
• sweeping the data over voltage and time to generate eye diagram data;
• detecting errors at identified cursors of the eye diagram data, wherein each identified cursor corresponds to a known multi-bit pattern within a set of previously transmitted bits;
• storing, in a data structure, counts of each detected error associated with a respective known bit pattern of the set of previously transmitted bits;
• and
• determining, by the processing device, based on the counts, a plurality of decision feedback equalizer (DFE) coefficients to be employed in receiving unknown data over the memory channel.