Clock generation circuitry
AssigneeCirrus Logic International Semiconductor Ltd.
InventorsLuis GOMEZ DURAN, Erich P. ZWYSSIG
Life of this patent
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Abstract
Clock generation circuitry configured to generate an output clock signal based on a reference clock signal, the clock generation circuitry comprising: monitoring circuitry for monitoring an offset between the output clock signal and the reference clock signal, wherein the clock generation circuitry is configured to adjust generation of the output clock signal based on the offset.
Claims20
Clock generation circuitry configured to generate an output clock signal based on a reference clock signal, the clock generation circuitry comprising:
- monitoring circuitry for monitoring an offset between the output clock signal and the reference clock signal,
- wherein the clock generation circuitry is configured to adjust generation of the output clock signal based on the offset.
A system comprising:
- a clock generation IC configured to:
- generate an output clock signal based on a reference clock signal;
- and
- generate an indication of a phase offset between the reference clock signal and the output clock signal;
- and
- controller circuitry, external to the clock generation IC configured to:
- receive the indication of the phase offset;
- and
- output a control signal based on the phase offset to the clock generation IC,
- wherein the clock generation IC is operative to adjust generation of the output clock signal based on the control signal.
Multi-mode clock generation circuitry configured to receive an input clock signal and generate an output clock signal, wherein the multi-mode clock generation circuitry is operable in:
- a first mode, in which a duration of a period of the output clock signal is adjusted based on an indication of an offset between the input clock signal and the output clock signal to compensate for the offset;
- and
- a second mode, in which generation of the output clock signal is adjusted based on the indication of the offset between the input clock signal and the output clock signal to compensate for the offset.
Dependencies are inferred from the claim text.