Digital phase-locked loop, electronic device, and method of operating digital phase-locked loop for tuning frequency and correcting phase error by using pulse signal-based variable capacitance

A method of operating a digital phase-locked loop, the method comprising:

• generating an up-down signal representing a result of a comparison of a phase of a reference signal and a phase of a feedback signal;
• generating, based on the up-down signal, an adjustment signal comprising digital code for adjusting a duty ratio for a first period corresponding to a period of the feedback signal;
• generating, based on the feedback signal, the adjustment signal, and the up-down signal, a capacitance control signal having the duty ratio;
• setting a first capacitance during a second period corresponding to the duty ratio of the capacitance control signal;
• adjusting a phase, based on inductance and an average of the first capacitance during the first period, to generate an output signal having the phase;
• and
• generating the feedback signal by dividing the output signal.

An electronic device for generating an output clock signal, based on a reference clock signal, the electronic device comprising:

• a phase detector configured to compare a phase of a reference clock signal and a phase of the feedback clock signal, and output an up-down signal representing a result of the comparison;
• a digital loop filter configured to output, based on the up-down signal, an adjustment signal comprising digital code for adjusting a duty ratio for a first period corresponding to a period of the feedback clock signal;
• a variable capacitance controller configured to output, based on the feedback clock signal, the adjustment signal, and the up-down signal, a capacitance control signal having the duty ratio;
• a digitally controlled oscillator configured to change capacitance of a capacitor bank circuit, based on the capacitance control signal, and adjust a phase of the output clock signal, based on an average of the capacitance during the first period;
• and
• a divider configured to generate the feedback clock signal by dividing the output clock signal.