Phase-locked loop and operating method thereof

A phase-locked loop comprising:

• a phase detection unit configured to detect a phase difference between a first clock and a second clock;
• a voltage generation unit configured to generate a control voltage in response to an output signal of the phase detection unit;
• an oscillating unit configured to generate the second clock that toggles at a frequency corresponding to a level of the control voltage;
• a clock division unit configured to generate a plurality of divided clocks by dividing the second clock at a plurality of ratios;
• and
• a lock detection unit configured to generate a first unlock signal using the phase difference between the first and second clocks on the basis of a first phase difference corresponding to a cycle of a selected divided clock among the plurality of divided clocks, to generate a second unlock signal using the phase difference between the first and second clocks on the basis of a second phase difference set by a plurality of delay cells, and to generate a lock completion signal in response to the first and second unlock signals.

An operating method of a phase-locked loop, comprising:

• generating a detection signal according to a result of detecting a phase difference between a first clock and a second clock;
• generating a control voltage in response to the detection signal;
• generating a third clock that toggles at a frequency corresponding to a level of the control voltage;
• generating a plurality of divided clocks by dividing the third clock at a plurality of ratios and outputting any one of the plurality of divided clocks as the second clock;
• activating a first unlock signal when the phase difference between the first and second clocks exceeds a first phase difference corresponding to a cycle of a selected divided clock among the plurality of divided clocks;
• activating a second unlock signal when the phase difference between the first and second clocks exceeds a second phase difference set by a plurality of delay cells;
• and
• generating a lock completion signal when both the first and second unlock signals are deactivated.