Current starved delay line bandwidth across process corners

A method of calibration in a delay locked loop (DLL), wherein the DLL includes a phase detector, a first delay path coupled between an input of the DLL and a first input of the phase detector, and a second delay path coupled between the input of the DLL and a second input of the phase detector, and wherein the first delay path includes a first delay circuit, and the second delay path includes a one-cycle delay circuit and a second delay circuit coupled in series, the method comprising:

• outputting a capacitive load control code to the first delay circuit, wherein the capacitive load control code controls capacitive loads of load capacitors in the first delay circuit;
• sweeping the capacitive load control code from a first value to a second value;
• recording a third value of the capacitive load control code at which an output of the phase detector indicates that a delay of the first delay path is approximately equal to a delay of the second delay path;
• and
• setting the capacitive load control code at the third value.