Source driver including 1-bit extended interpolation amplifier

A source driver comprising:

• an interpolation amplifier configured to receive a plurality of input voltages repeatedly, the plurality of input voltages including at least one of a first gamma voltage or a second gamma voltage having a voltage level different from that of the first gamma voltage, and configured to generate an output voltage corresponding to interpolation data of N bits (N is a natural number of 2 or more) based on the plurality of input voltages, wherein
• the interpolation amplifier includes a plurality of differential input pairs less than 2N,
• the plurality of differential input pairs are configured to receive the plurality of input voltages,
• the plurality of differential input pairs include
• a first differential input pair including a first input transistor configured to receive a first input voltage of the plurality of input voltages,
• a second differential input pair including a second input transistor configured to receive a second input voltage of the plurality of input voltages, and
• a third differential input pair including a third input transistor configured to receive a third input voltage of the plurality of input voltages, and
• a ratio of a channel width to a channel length of each of the first input transistor and the second input transistor is less than that of the third input transistor.

A source driver comprising:

• an input voltage selector configured to receive a first gamma voltage, a second gamma voltage having a voltage level different from that of the first gamma voltage, and interpolation data, and configured to output a plurality of input voltages in accordance with the interpolation data and based on the first and second gamma voltages;
• and
• an interpolation amplifier including a first input circuit including a first differential input pair configured to receive a first input voltage of the plurality of input voltages and a first current source configured to generate a first bias current, and a second input circuit including a second differential input pair configured to receive a second input voltage of the plurality of input voltages and a second current source configured to generate a second bias current, wherein
• a ratio of a channel width to a channel length of a first input transistor of the first differential input pair is less than that of a second input transistor of the second differential input pair,
• the first input transistor is configured to receive the first input voltage,
• the second input transistor is configured to receive the second input voltage, and
• a magnitude of the first bias current is less than a magnitude of the second bias current.