Balancer of electric double-layer capacitor

Abstract

Disclosed is a balancer for electric double-layer capacitors that maximizes charging energy efficiency by allowing deviation within a permissible range in which charging voltages of a first electric double-layer capacitor and a second electric double-layer capacitor do not cause problems, while controlling currents flowing through the two electric double-layer capacitors to be equal. The balancer includes a first resistor, a second resistor, and a third resistor sequentially connected in series between a power line and a common line; a first transistor having a base terminal electrically connected between the first resistor and the second resistor and connected in parallel with the first electric double-layer capacitor; and a second transistor connected in series with the first transistor, having a base terminal electrically connected between the second resistor and the third resistor and connected in parallel with the second electric double-layer capacitor.

Dependencies are inferred from the claim text.