Test circuit and semiconductor apparatus including the same
AssigneeSK hynix Inc.
InventorJae Yong KANG
Life of this patent
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Abstract
A test circuit includes a data compression circuit and an output control circuit. The data compression circuit compresses read data transmitted through a plurality of first signal lines to generate a plurality of test result signals and outputs the plurality of test result signals through a plurality of second signal lines. The output control circuit selects one of the plurality of test result signals and the read data in accordance with die identification information and a test mode signal, and sequentially outputs the selected signal through a preassigned pad, among a plurality of pads.
Claims16
A test circuit, comprising:
- a data compression circuit configured to compress read data transmitted through a plurality of first signal lines to generate a plurality of test result signals and configured to output the plurality of test result signals through a plurality of second signal lines;
- and
- an output control circuit configured to select one of the plurality of test result signals and the read data in accordance with die identification information and a test mode signal and configured to sequentially output the selected signal through a preassigned pad, among a plurality of pads.
A semiconductor apparatus, comprising:
- a plurality of unit memory regions;
- a plurality of normal global lines coupled in common with the plurality of unit memory regions;
- a data compression circuit configured to compress read data transmitted through the plurality of normal global lines to generate a plurality of test result signals and configured to output the plurality of test result signals through a plurality of test global lines;
- and
- an output control circuit configured to select one of the plurality of test result signals and the read data in accordance with die identification information and a test mode signal and configured to sequentially output the selected signal through a preassigned pad, among a plurality of pads.
A semiconductor apparatus, comprising a plurality of semiconductor dies, each having a plurality of pads coupled to each other through bonding wires, and configured such that when a test read command is input, the plurality of semiconductor dies simultaneously output test results through some of the plurality of pads in different order.
Dependencies are inferred from the claim text.