Memory with Input Data Storage Circuits for Redundancy Shift and Store

A method of using a first input data path in a memory to receive column redundancy address signals, comprising:

• shifting a first column redundancy address signal from a first master latch in a first master-slave latch to a first slave latch in the first master-slave latch to latch the first column redundancy address signal in the first slave latch;
• configuring the first input data path to couple from the first master latch to a first write driver responsive to the first column redundancy address signal latched in the first slave latch;
• latching a first input data signal in the first master latch;
• coupling the first input data signal from the first master latch through the first input data path to the first write driver;
• and
• driving the first input data signal from the first write driver to a selected column of bitcells from a first multiplexed group of columns of bitcells.

A memory, comprising:

• a first global input/output column group;
• a second global input/output column group;
• a scan chain including a plurality of master-slave latches arranged serially starting from a first master-slave latch;
• a first global input/output circuit including a data input latch, wherein the data input latch is configured to function as a master latch in the first master-slave latch;
• a first multiplexer configured to select between a data input signal and a serialized decoded column redundancy address signal, wherein the first multiplexer includes an output terminal coupled to a data input terminal of the data input latch, and wherein a slave latch in the first master-slave latch is configured to latch a column redundancy address signal from the serialized decoded column redundancy address signal;
• and
• a data path configured to couple from an output terminal of the data input latch to a selected one of the first global input/output column group and the second global input/output column group according to a column redundancy selection that is responsive to the column redundancy address signal.