Memory circuit and information processing apparatus
AssigneeFujitsu Limited
InventorKenji GOTO
Life of this patent
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Abstract
A memory circuit including a word line driver configured to set a potential of a word line signal input to a selected memory cell to a second value lower than a first value by a certain amount until a stable operation of the memory cell is ensured, a timing adjustment circuit configured to determine a time at which the potential of the word line signal is set to the second value, and a pull-up circuit configured to boost the potential of the word line signal from the second value to the first value according to the determined time.
Claims10
A memory circuit comprising:
- a word line driver configured to set a potential of a word line signal input to a selected memory cell to a second value lower than a first value by a certain amount until a stable operation of the memory cell is ensured;
- a timing adjustment circuit configured to determine a time at which the potential of the word line signal is set to the second value;
- and
- a pull-up circuit configured to boost the potential of the word line signal from the second value to the first value according to the determined time.
An information processing apparatus comprising a processor and a memory having a memory circuit,
- wherein the memory circuit includes:
- a word line driver configured to set a potential of a word line signal input to a selected memory cell to a second value lower than a first value by a certain amount until a stable operation of the memory cell is ensured;
- a timing adjustment circuit configured to determine a time at which the potential of the word line signal is set to the second value;
- and
- a pull-up circuit configured to boost the potential of the word line signal from the second value to the first value according to the determined time.
Dependencies are inferred from the claim text.