Techniques for read burst ordering control at a memory system
AssigneeMicron Technology, Inc.
InventorJongtae Kwak
Life of this patent
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Abstract
Methods, systems, and devices for techniques for read burst ordering control at a memory system are described. The described techniques provide for a memory system to output offset data read signals according to activation of either a count start even signal or a count start odd signal. A first control circuit may receive the count start odd signal at a data input and the count start even signal at a set/reset input, and a second control circuit may receive the count start even signal at a data input and the count start odd signal at a set/reset input. Based on the values of the count start even signal and the count start odd signal, one of the shift register outputs may be delayed relative to the other shift register output.
Claims20
A memory system, comprising:
- a memory device;
- a receiver circuit configured to:
- receive a read command to retrieve data;
- identify whether the read command is received before one of a rising or falling edge of a first clock signal of a divided clock or before one of a rising or falling edge of a second clock signal of the divided clock;
- and
- initiate a signal based at least in part on the read command being received before the rising or falling edge of the first clock signal or the rising or falling edge of the second clock signal;
- and
- a clock circuit configured to generate two data read signals to control burst ordering for transmitting the data based at least in part on the signal, the clock circuit comprising a first shift register to generate a first data read signal and a second shift register to generate a second data read signal, wherein the output of the first shift register or the second shift register is configured to be delayed relative to the other shift register based at least in part on whether the read command is received before the rising or falling edge of the first clock signal or the rising or falling edge of the second clock signal.
A method by a memory system, comprising:
- receiving, by a receiver circuit, a read command to retrieve data;
- identifying, by the receiver circuit, whether the read command is received before one of a rising or falling edge of a first clock signal of a divided clock or before one of a rising or falling edge of a second clock signal of the divided clock;
- initiating, by the receiver circuit, a signal based at least in part on the read command being received before the rising or falling edge of the first clock signal or the rising or falling edge of the second clock signal;
- and
- generating, by a clock circuit, two data read signals to control burst ordering for transmitting the data based at least in part on the signal, the clock circuit comprising a first shift register to generate a first data read signal and a second shift register to generate a second data read signal, wherein the output of the first shift register or the second shift register is configured to be delayed relative to the other shift register based at least in part on whether the read command is received before the rising or falling edge of the first clock signal or the rising or falling edge of the second clock signal.
A memory system, comprising:
- a memory device;
- and
- processing circuitry coupled with the memory device and configured to cause the memory system to:
- receive a read command to retrieve data;
- identify whether the read command is received before one of a rising or falling edge of a first clock signal of a divided clock or before one of a rising or falling edge of a second clock signal of the divided clock;
- initiate a signal based at least in part on the read command being received before the rising or falling edge of the first clock signal or the rising or falling edge of the second clock signal;
- and
- generate two data read signals to control burst ordering for transmitting the data based at least in part on the signal, the memory system comprising a first shift register to generate a first data read signal and a second shift register to generate a second data read signal, wherein the output of the first shift register or the second shift register is configured to be delayed relative to the other shift register based at least in part on whether the read command is received before the rising or falling edge of the first clock signal or the rising or falling edge of the second clock signal.
Dependencies are inferred from the claim text.