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US 2026/0161572 A1Published application
Power-aware cache replacement policy
AssigneeQUALCOMM Incorporated
InventorsHiral NANDU, Subbarao PALACHARLA, Vinod Mohan GEORGE, Tarun SOLANKI, Prathamesh Dilip PATEL
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Abstract
A processor-implemented method for power-aware cache replacement includes receiving a request associated with a data transaction directed to a cache memory. A cache miss is determined to have occurred based on the data transaction. A portion of the cache memory is allocated for replacement in accordance with the data transaction based on a power state of the portion of the cache memory.
Claims20
An apparatus, comprising:
- at least one memory;
- and
- a memory management unit coupled to the at least one memory, the memory management unit configured to:
- receive a request associated with a data transaction directed to a cache memory of the at least one memory;
- determine that a cache miss has occurred based on the data transaction;
- and
- allocate a portion of the cache memory for replacement in accordance with the data transaction based on a power state of the portion of the cache memory, by prioritizing allocation to a first portion in an active power state over a second portion in a sleep retention power state, the allocation occurring responsive to the cache miss.
4 more elements
A processor-implemented method performed by one or more processors, the processor-implemented method, comprising:
- receiving a request associated with a data transaction directed to a cache memory of the at least one memory;
- determining that a cache miss has occurred based on the data transaction;
- and
- allocating a portion of the cache memory for replacement in accordance with the data transaction based on a power state of the portion of the cache memory, by prioritizing allocation to a first portion in an active power state over a second portion in a sleep retention power state, the allocation occurring responsive to the cache miss.
1 more element
An apparatus, comprising:
- means for receiving a request associated with a data transaction directed to a cache memory of the at least one memory;
- means for determining that a cache miss has occurred based on the data transaction;
- and
- means for allocating a portion of the cache memory for replacement in accordance with the data transaction based on a power state of the portion of the cache memory, by prioritizing allocation to a first portion in an active power state over a second portion in a sleep retention power state, the allocation occurring responsive to the cache miss.
1 more element
Dependencies are inferred from the claim text.