Slot/sub-slot prefetch architecture for multiple memory requestors
AssigneeTexas Instruments Incorporated
InventorsKai CHIRCA, Joseph R. M. ZBICIAK, Matthew D. PIERSON
Life of this patent
Estimating the term…
Abstract
An example device includes multiple memories; and a memory controller coupled to the multiple memories. The memory controller includes a detection filter that includes a set of address slots and a set of direction prediction fields, each of which is associated with a respective one of the address slots. The memory controller further includes a buffer that includes a set of buffer slots, each of which includes an address field, a direction prediction field, a data pending field, a data valid field, and a set of sub-slots to store data. Each address field of each slot of the set of buffer slots stores at least a portion of an address associated with the corresponding slot.
Claims16
A device comprising:
- multiple memories;
- and
- a memory controller coupled to the multiple memories, the memory controller including:
- a detection filter that includes a first set of address slots and a set of direction prediction fields, each of which is associated with a respective one of the address slots of the first set of address slots;
- and
- a buffer that includes a set of buffer slots, each slot of the set of buffer slots including an address field, a direction prediction field, a data pending field, a data valid field, and a set of sub-slots configured to store data, wherein each address field of each slot of the set of buffer slots is configured to store at least a portion of an address associated with the corresponding slot.
A method comprising:
- receiving, by a memory controller, a first request for data;
- providing the first request to one of multiple memories coupled to the memory controller;
- determining, by the memory controller based on an address associated with the first request, that the first request is a miss in a detection filter;
- predicting, by the memory controller, a first stream direction for the first request;
- predicting, by the memory controller, a next address for the first request based on the first stream direction;
- and
- storing the next address for the first request in the detection filter.
Dependencies are inferred from the claim text.