Decoupled ordered micro sequencer
AssigneeIntel Corporation
InventorsMuhammad Faisal Azeem, Joju Joseph Zajo, Malihe Ahmadi, Xiang Zou, Rangeen Basu Roy Chowdhury
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Abstract
Methods and apparatus relating to a decoupled ordered micro sequencer are described. In an embodiment, a processor includes a decoder and a Micro Sequencer Unit (MSU). The MSU receives a decode request for an instruction from the decoder in response to a determination by the decoder that the instruction is complex. The decode request includes additional information to allow the MSU to decode the instruction without further communication with the decoder. Other embodiments are also disclosed and claimed.
Claims20
A processor comprising:
- a decoder to receive an instruction;
- and
- a Micro Sequencer Unit (MSU) to receive a decode request for the instruction from the decoder in response to a determination by the decoder that the instruction is complex,
- wherein the decode request is to include additional information to allow the MSU to decode the instruction without further communication with the decoder.
One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to cause:
- a decoder to receive an instruction;
- and
- a Micro Sequencer Unit (MSU) to receive a decode request for the instruction from the decoder in response to a determination that the instruction is complex,
- wherein the decode request is to include additional information to allow the MSU to decode the instruction without further communication with the decoder.
Dependencies are inferred from the claim text.