Ferroelectric iii-nitride layer thickness scaling

A heterostructure comprising:

• a template layer;
• a ferroelectric semiconductor layer supported by the template layer;
• and
• a conductive layer adjacent to a side of the ferroelectric layer opposite the template layer;
• wherein:
• the ferroelectric semiconductor layer comprises an alloy of a III-nitride material;
• the alloy comprises a Group IIIB element;
• the ferroelectric semiconductor layer is in contact with the template layer;
• and
• the side of the ferroelectric semiconductor layer has a native oxide layer with a thickness no greater than about 1 nm.

A method of forming a heterostructure, the method comprising:

• providing a template layer of the heterostructure, the template layer being supported by a substrate;
• implementing a surface treatment procedure to remove oxide from a surface of the template layer;
• after implementing the surface treatment procedure, implementing a non-sputtered, epitaxial growth procedure to form a ferroelectric semiconductor layer of the heterostructure, the ferroelectric semiconductor layer being supported by, and in contact with, the template layer;
• and
• depositing a conductive layer adjacent to a side of the ferroelectric layer opposite the template layer;
• wherein:
• the ferroelectric semiconductor layer comprises an alloy of a III-nitride material;
• the non-sputtered, epitaxial growth procedure is configured to incorporate a group IIIB element into the alloy of the III-nitride material;
• and
• depositing the conductive layer is implemented such that exposure of the ferroelectric semiconductor layer to an ambient between the non-sputtered, epitaxial growth procedure and deposition of the conductive layer is limited to a time period such that a thickness of a native oxide layer disposed between the conductive layer and the ferroelectric semiconductor layer has a thickness no greater than about 1 nm.

A heterostructure comprising:

• a template layer;
• and
• a ferroelectric semiconductor layer supported by the template layer, the ferroelectric semiconductor layer being single-crystalline;
• wherein:
• the ferroelectric semiconductor layer comprises an alloy of a III-nitride material;
• the alloy comprises a Group IIIB element;
• the ferroelectric semiconductor layer is in contact with the template layer;
• and
• the ferroelectric semiconductor layer has a thickness less than 10 nm.

A heterostructure comprising:

• a template layer;
• and
• a ferroelectric semiconductor layer supported by the template layer, the ferroelectric semiconductor layer being single-crystalline;
• wherein:
• the ferroelectric semiconductor layer comprises an alloy of a III-nitride material;
• the alloy comprises a Group IIIB element;
• the ferroelectric semiconductor layer has a thickness less than 100 nm;
• and
• the ferroelectric semiconductor layer is in contact with the template layer such that a coercive field of the ferroelectric semiconductor layer is a function of a lattice mismatch between the template layer and the ferroelectric semiconductor layer.

A method of forming a heterostructure, the method comprising:

• providing a template layer of the heterostructure, the template layer being supported by a substrate;
• implementing a surface treatment procedure to remove oxide from a surface of the template layer;
• after implementing the surface treatment procedure, implementing a non-sputtered, epitaxial growth procedure to form a ferroelectric semiconductor layer of the heterostructure, the ferroelectric semiconductor layer being supported by, and in contact with, the template layer;
• and
• depositing a conductive layer adjacent to a side of the ferroelectric layer opposite the template layer;
• wherein:
• the ferroelectric semiconductor layer comprises an alloy of a III-nitride material;
• the non-sputtered, epitaxial growth procedure is configured to incorporate a group IIIB element into the alloy of the III-nitride material;
• and
• the conductive layer is deposited in situ such that the ferroelectric semiconductor layer is not exposed to an ambient between the non-sputtered, epitaxial growth procedure and deposition of the conductive layer.