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US 2026/0157239 A1Published application
Stacked memory devices and semiconductor system
AssigneeSK hynix Inc.
InventorsJoon Yong CHOI, Choung Ki SONG, Jong Moo LEE
Life of this patent
Estimating the term…
Abstract
A semiconductor system including a control device including a first area and a second area. The first area includes an internal interface area disposed in a first direction and the second area comprising an internal input and output line disposed in a second direction. The control device includes a memory device stacked on the second area and configured to input and output data. The internal interface area intersecting with the internal input and output line. The control device and the memory device are configured to input and output the data to and from the internal interface area through the internal input and output line.
Claims26
A semiconductor system comprising:
- a control device including a first area and a second area, the first area comprising an internal interface area disposed in a first direction and the second area comprising an internal input and output line disposed in a second direction;
- and
- a memory device stacked on the second area and configured to input and output data,
- wherein the internal input and output line intersects with the internal interface area to connect to the interface area and the intersection of the internal input and output line with the internal interface area is substantially orthogonal,
- wherein the control device and the memory device are configured to input and output the data to and from the internal interface area through the internal input and output line, and
- a setting space is set vertically to the first area.
3 more elements
A semiconductor system comprising:
- a control device including first to third areas, the first area comprising a first internal interface area disposed in a first direction, the second area comprising first and second internal input and output lines disposed in a second direction, and the third area comprising a second internal interface area disposed in the first direction;
- and
- a memory device stacked on the second area and configured to input and output first and second data,
- wherein the first and second internal interface areas and the first and second internal input and output lines are connected in an orthogonal direction to each other,
- wherein the control device and the memory device are configured to input and output the first and second data to and from the first and second internal interface areas through the first and second internal input and output lines,
- a first setting space is set vertically to the first area,
- a second setting space is set vertically to the second area, and
- a third setting space is set vertically to the third area.
5 more elements
A semiconductor system comprising:
- a control device including a first area and a second area, the first area comprising an internal interface area disposed in a first direction and the second area comprising first and second internal input and output lines disposed in a second direction;
- and
- a memory device stacked on the second area and configured to input and output data,
- wherein the internal interface area and the first and second internal input and output lines are connected in an orthogonal direction to each other,
- wherein the control device and the memory device are configured to input and output the data to and from the internal interface area through the first and second internal input and output lines,
- a first setting space is set vertically to the first area, and
- a second setting space is set vertically to the second area.
4 more elements
A semiconductor system comprising:
- a control device including first to third areas, the first area comprising a first internal interface area disposed in a first direction, the second area comprising an internal input and output line disposed in a second direction, and the third area comprising a second internal interface area disposed in the first direction;
- and
- a memory device stacked on the second area and configured to input and output first and second data,
- wherein the first and second internal interface areas and the internal input and output line are connected in an orthogonal direction to each other,
- wherein the control device and the memory device are configured to input and output the first and second data to and from the first and second internal interface areas through the internal input and output line,
- a first setting space is set vertically to the first area,
- a second setting space is set vertically to the second area, and
- a third setting space is set vertically to the third area.
5 more elements
Dependencies are inferred from the claim text.