Nonvolatile memory device and electronic system including the same

A non-volatile memory device comprising:

• a first substrate;
• a gate stack structure comprising interlayer insulating layers and gate electrodes stacked in an alternating fashion on a lower surface of the first substrate;
• channel structures extending through the gate stack structure in a first direction perpendicular to the lower surface of the first substrate;
• a first bonding portion below the channel structures and connected to at least one of the channel structures;
• a second substrate facing the first substrate in the first direction;
• a first circuit element on an upper surface of the second substrate;
• a third substrate between the first substrate and the second substrate;
• a second circuit element on the third substrate;
• a second bonding portion on the second circuit element, the second bonding portion being in contact with the first bonding portion;
• a through structure comprising a dummy semiconductor pattern spaced apart from the third substrate, and a through electrode extending through the dummy semiconductor pattern in the first direction and toward the upper surface of the second substrate;
• and
• a barrier pattern extending through the third substrate in the first direction and surrounding a side surface of the through structure,
• wherein the through electrode has a first end connected to the first circuit element and a second end connected to the second circuit element or at least one of the second bonding portions.

An electronic system comprising:

• a main substrate;
• a non-volatile memory device on the main substrate;
• and
• a controller electrically connected to the non-volatile memory device, the controller being on the main substrate,
• wherein the non-volatile memory device comprises:
• a first substrate;
• a plurality of memory cell structures on the first substrate;
• a second substrate facing the first substrate in a first direction perpendicular to a surface of the first substrate;
• a first circuit element on the second substrate;
• a third substrate between the first substrate and the second substrate;
• a second circuit element on the third substrate;
• and
• a through structure comprising
• a dummy semiconductor pattern that is surrounded by the third substrate and spaced apart from the third substrate, and
• a through electrode extending through the dummy semiconductor pattern in the first direction,
• wherein the through electrode has a first end connected to the first circuit element and a second end connected to the second circuit element or at least one of the memory cell structures.